1. Field of the Invention
The present invention relates to plasma screens and more specifically to the control of cells of a plasma screen.
2. Discussion of the Related Art
A plasma screen is an array type screen formed of cells arranged at the intersections of lines and columns. A cell includes a cavity filled with a rare gas, and at least two control electrodes. To create a light point on the screen, by using a given cell, the cell is selected by applying a potential difference between its control electrodes, after which the cell gas is ionized, generally by means of a third control electrode. This ionization goes along with an emission of ultraviolet rays. The creation of the light point is obtained by excitation of a red, green or blue luminescent material by the emitted rays.
FIG. 1 shows a conventional structure of a plasma screen formed of cells 4. Each cell 4 has two control electrodes respectively connected to a line 6 and to a column 8.
The selection of the cells, to create images, is performed, conventionally, by logic circuits generating control signals. The logic states of these signals determine the cells that are controlled to generate a light point and those that are controlled not to generate one. The ionization of a gas of a cell requires that potentials on the order of some hundred volts be applied between the two control electrodes for a predetermined duration, on the order of 2 microseconds. Each cell has an equivalent capacitance on the order of several tens of picofarads.
FIG. 2 shows a plasma screen, the cells 4 of which are represented by an equivalent capacitor. A line control circuit 10 includes, for each line 6, a line control block 14, an output of which is connected to line 6. A column control circuit 12 includes, for each column 8, a column control block 18, an output 20 of which is connected to column 8. Circuits 10 and 12 are generally integrated on a same semiconductor chip.
Conventionally, the cells of a plasma screen are activated line by line. The non-activated lines are set to a quiescent voltage VDD1 (for example, 150 V). The activated line is brought to an activation voltage GND (0 V). To light chosen points of the activated line, the corresponding columns are brought to a voltage VDD2 (80 V). The columns corresponding to the other points of the activated line are brought to voltage GND (0 V). Thus, the lit cells of the activated line see a column-line voltage equal to VDD2−GND (80 V) and the unlit cells of the activated line see a column-line voltage equal to GND−GND (0 V). For all non-activated lines, the line voltage is VDD1 (150 V) and the column voltage is 0 or 80 V. In both cases, the cells of the non-activated lines are reverse biased.
Each line control block 14 includes a pair of complementary power transistors 22 and 24. Transistor 24 receives voltage VDD1 on its source. Its drain is connected to a line 6 and its gate receives a line deactivation control signal LSN. The source of transistor 22 is connected to voltage GND. Its drain is connected to line 6 and its gate receives a control signal LS complementary to signal LSN. Signals LS and LSN are generated, for example, by a microprocessor, not shown.
Each column control block 18 includes an output stage 26 including a couple of power transistors (not shown) enabling bringing output 20 to voltages VDD2 or GND according to a logic column selection signal LCS provided to stage 26. Each control block 18 also includes a memory element 28 connected, for example, to a microprocessor, not shown, for receiving and storing the value of logic signal LCS intended for output stage 26. Each control block 18 further includes a logic switch 30 controlled by an enable signal VAL, connected between memory element 28 and output stage 26. Logic switch 30 is provided to provide an inactive signal to output stage 26 as long as enable signal VAL is inactive, for example at a low logic level. Switch 30 is also provided for, when signal VAL is active, providing output stage 26 with signal LCS stored in memory element 28. Signal VAL is conventionally activated for a predetermined duration after each activation of a screen line.
FIG. 3 is a timing diagram illustrating voltage V6 of a line 6, enable signal VAL, voltage V8 of a column 8, and current I22 in transistor 22 of line control circuit 14. At a time t0, the line is selected and voltage V6 switches from voltage VDD1 to voltage GND. Voltage V8 then is at GND. At a time t1, signal VAL is activated and column 8 is connected to potential VDD2, for a point to be lit. The selected cell charges between time t1 and a time t2 and voltage V8 switches from GND to VDD2. During this charge, transistor 22 conducts a first current peak P1. For physical reasons associated with the cell structure, a short time after this first current peak, a second current peak P2, more intense than the first one, occurs between times t3 and t4. As an example, time t1 may occur from 10 to 20 ns after time t0, time t2 may occur from 50 to 100 ns after time t1, and times t3 and t4 may occur from 150 to 200 ns after times t1 and t2, respectively. The charge of a cell can correspond to current peaks P1 and P2 respectively of 0.1 and 0.3 mA. A control circuit is conventionally used to control more than 3000 columns. Thus, if all the columns 8 of a selected line must be lit, the second current peak crossing transistor 22 can reach 1 A. Transistors 22 must have a large size to be able to conduct such a current.